High performance arrays in an integrated circuit system, such as an SRAM in a processor system, typically use a local clock generator circuit to control the internal circuit timing of the array. Such array local clock generators (also referred to as a Local Clock Buffer or LCB) are used to control critical circuit functions of the array, such as word decode/bit decode and read/write functions. In order to provide flexibility in tuning the timing of the array circuit function and an ability to change the array circuit timing as part of a hardware debugging process, a state of the art LCB will often have a programmable control circuit that can alter the delay of the local clock relative to the system clock and can alter the local clock pulse width. In the prior art, a programmable control input to an explicit decoder typically selects the number of elements in an inverter delay chain. Discreet decoders and separate discreet delay chains used in the prior art result in a Local Clock Buffer that is complex, requires a substantial area of the chip to implement, and requires substantial power to operate.